The invention relates to a fuse circuit configuration formed of a series circuit composed of a first switching transistor, a second switching transistor, and a fuse. An evaluation circuit is connected at a junction between the two switching transistors, it being possible to store the state of the fuse at the output of the evaluation circuit. Fuse circuit configurations such as fuse latches are preferably utilized for redundancy, chip identification and various other settings in conventional memories such as DRAMs, FeRAMs, flashes and so on.
It is accordingly an object of the invention to provide a fuse circuit configuration that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which practically excludes the possibility of misevaluations due to parasitic capacitors.
With the foregoing and other objects in view there is provided, in accordance with the invention, a fuse circuit configuration. The fuse circuit configuration contains a first switching transistor and a second switching transistor disposed in series with the first switching transistor and defines a series circuit with a junction point disposed between the first switching transistor and the second switching transistor. A fuse is connected to the second switching transistor. An evaluation circuit is connected to the junction point and has an output at which a status of the fuse can be tapped. A compensation capacitor is connected to the junction point and counteracts a parasitic capacitor occurring between a connection point between the second switching transistor and the fuse on a first side and ground on a second side.
The object is inventively achieved in a fuse configuration of the above mentioned type by a compensation capacitor which is connected to the junction and which counteracts a parasitic capacitor arising between the connection between the second switching transistor and the fuse, on one side, and ground, on the other side. The compensation capacitor can simulate the layout of the connection between the second switching transistor and the fuse.
In the inventive fuse circuit configuration, a compensation capacitor is provided at the junction between the two switching transistors. The compensation capacitor is initially charged to a high potential. The required charging current for the parasitic capacitor can thereby be drawn from the compensation capacitor without having to fear a tipping of the latch. For reasons of space, the compensation capacitor should not be proportioned too large.
Rather, the compensation capacitor should have the same value (i.e. capacitance) as the parasitic capacitor. This can be accomplished by also simulating the layout of the connection between the second switching transistor and the fuse in the connection between the junction and the latch. In other words, the layout of the fuse configuration is repeated in the evaluation circuit to the greatest extent possible in order to generate the compensation capacitor that counteracts the parasitic capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a fuse circuit configuration. The fuse circuit configuration contains a a first switching transistor and a second switching transistor disposed in series with the first switching transistor and defines a series circuit with a junction point disposed between the first switching transistor and the second switching transistor. A fuse is connected to the second switching transistor. An evaluation circuit is connected to the junction point and has an output at which a status of the fuse can be tapped. A ground terminal is provided and a compensation capacitor is connected between the junction point and the ground terminal. The compensation capacitor delivers a charging current for a parasitic capacitor occurring between a connection between the second switching transistor and the fuse on a first side and the ground terminal on a second side.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a fuse circuit configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.